DRAM Architecture
DRAM chips are large, rectangular arrays of
member cells with support logic, which reads and writes data in the arrays, and
refresh circulatory to maintain the integrity of stored data. The memory cells
are arranged in rows and columns. The memory cells arranged in rows are called word
lines and the memory cells that are arranged in the columns are called bit
lines. A DRAM memory cell is a capacitor that is charged to produce a 1 or
0. DRAM stores
programs and data in 8-bit (1-byte) chunks of memory.
Eight 1-bit wide DRAMs make one 8-bit wide DRAM.
Trenches filled with dielectric material are
used to create the capacitive storage element of the memory cell.
A figure of an IBM Trench Capacitor Memory
Cell
The support circuitry of the memory
chip of a DRAM allows the user to read the data stored in the memory cells,
write to the memory cells and refresh memory cells.
The Support Circuitry includes the following
parts:
- Address logic The addresses are used to select
a memory location on the chip. It is also used for both row and column
address selection (multiplexing). The voltage levels present at the time
that /RAS or /CAS goes active determines the row or column address,
respectively that is selected.
- Sense Amplifiers to amplify the signal or
charge that is detected on a memory cell.
- Row Address Select (/RAS) is
used to latch and resolve the row addresses and to initiate and terminate
read and write operations. During a complete memory
cycle, there is a minimum amount of time that /RAS must be active (tRAS),
and a minimum amount of time that /RAS must be inactive, called the /RAS
precharge time (tRP).
/RAS may also be used to trigger a refresh cycle (/RAS Only Refresh, or ROR).
- Column Address Select (Strobe) (/CAS) /CAS
is used to latch the column address and to initiate the read or write
operation. /CAS may also be used to trigger a /CAS before /RAS refresh
cycle. This refresh cycle requires /CAS to be active prior to /RAS and to
remain active for a specified time. It is active low. For most memory
operations, there is also a minimum amount of time that /CAS must be
inactive, called the /CAS precharge time (tCP).
(An ROR cycle does not require /CAS to be active.)
- Read and write Circuitry to
store information in the memory’s cells and read those that are stored.
- Write Enable (/WE) The write enable
signal is used to choose a read operation or a write operation. A low
voltage level signifies that a write operation is desired; a high voltage level
is used to choose a read operation. To ensure that the correct operation
is selected, set up and hold times with respect to /CAS is specified in
the DRAM timing specification.
- Output Enable (/OE) During a read
operation, this control signal is used to prevent data from appearing at
the output until needed. When /OE is low, data appears at the data outputs
as soon as it is available. /OE is ignored during a write operation. In
many applications, the /OE pin is grounded and is not used to control the DRAM
timing.
- Data In or Out (DQs) The DQ pins (also
called Input/Output pins or I/Os) on the memory device are used for input
and output. During a write operation, a voltage (high=1, low=0) is applied
to the DQ. This voltage is translated into the appropriate signal and
stored in the selected memory cell. During a read operation, data read
from the selected memory cell appears at the DQ once access is complete
and the output is enabled (/OE low). At most other times, the DQs are in a
high impedance state; they do not source or sink any current, and do not
present a signal to the system. This also prevents DQ contention when two
or more devices share the data bus.
- Internal Counters or Registers to
keep track of the refresh sequence, or to initiate refresh cycles as
needed.
Internal Diagram of a DRAM Chip