EISA(Extended Industry Standard Architecture)

 

EISA is a superset of the ISA 8 and 16-bit architecture, extending the capabilities of ISA while still maintaining compatibility with ISA expansion boards.

 

Introduction

 

With the advent of the '386 processor introduced in 1987 by Intel, the various competing PC manufactures, IBM, clones, etc, now split ranks and independently designed several different architectures which competed with each other. IBM developed Micro Channel Architecture or the MCA slot. MCA architecture was advanced and fast ,at 32 bits per clock tick. IBM asked the clone manufacturers for a licensing fee in order to use MCA architecture, but they all refused. Instead, nine IBM competitors (sometimes called the Gang of Nine): AST Research, Compaq Computer, Epson, Hewlett-Packard, NEC, Olivetti, Tandy, WYSE, and Zenith Data Systems decided to design their own architecture around the Intel '386 chip. Compaq avoided the two key mistakes that IBM made when they developed EISA. First, they made it compatible with the ISA bus. Second, they opened the design to all manufacturers instead of keeping it proprietary, by forming the non-profit EISA committee to manage the design of the standard. A year later, in 1988, EISA buses started to show up on clone computers.

Unfortunately, motherboard manufacturers discovered that EISA architecture and their ensuing EISA architecture peripheral cards were much more costly to produce than an ISA card was. In nowadays, the performance of EISA bus is quite low compared to the popular local buses like the VESA Local Bus and PCI.  EISA architecture fell out of favor for the general PC market and can only be found now in server PCs and higher-end PCs. EISA was similar to MCA both in terms of technology and market acceptance: it had significant technical advantages over ISA, and it never caught on with the PC-buying public.

 

This is the EISA bus, introduced in 1987 as a competitor to the MCA Bus.

 

This picture shows a comparison of the EISA and ISA bus connectors

 

Features

 

The principal difference between EISA and MCA was that EISA is backward compatible with the ISA bus, while MCA is not. This means that computers with an EISA bus can use new EISA expansion cards as well as old ISA expansion cards. Computers with an MCA bus can use only MCA expansion cards. 

EISA features include,

·                     32-bit data transfers

·                     33 MB maximum bandwidth

·                     32-bit memory addressing, providing up to 4GB of addressable memory space (as with the ISA extension, the extra address lines were not latched providing for faster addressing).

·                     Multiple Bus masters

·                     Programmable level or edge-triggered interrupts (with a number of devices being able to share the same interrupt in the case of level-triggered interrupts).

·                     Automatic board configuration.

Increased data throughput is mainly due to the bus doubling in size.  However, in order to take full advantage of the higher performance level of the EISA bus, one would need to use expansion cards that utilize the additional pins.  EISA slots look like this:

Diagram of 16-bit EISA bus

While an ISA slot looks like this:
Diagram of 8-bit ISA bus

An important feature of the EISA bus is that the host or any bus master can access any memory device or peripheral in the system, even if their bus widths differ. As indicated in the features list, for sheer speed EISA excelled providing a maximum 32-bit data transfer rate of 33 MB/s. While EISA supports level-triggered interrupt lines, it is important to note that older ISA cards cannot share interrupts even when plugged into an EISA connector, since they rely on older edge-triggering.

Bus master support in the EISA could be described as complete as opposed to that provided in the ISA bus. The memory refresh controller, the active DMA channel with the highest priority and peripherals vying for bus control compete for ownership of the bus by means of a three-way sharing scheme controlled by the EISA arbitration unit, the Integrated System Peripheral chip. The scheme ensures that no bus master is deprived access although it is possible for low-priority DMA channels to suffer. An additional watchdog on the system is provided by the Intel's Bus Master Interface Chip (BMIC) which ensures that no one master remains in control of the bus for too long. After a certain time period elapses, the master is removed from the bus and a non-maskable interrupt is generated by the CPU.

 

 Differences between ISA and EISA Architectures.

EISA introduced the following improvements over ISA:

 

·                     Supports intelligent bus master expansion cards.

·                     Improved bus arbitration and transfer rates.

·                     Facilitates 8, 16 or 32-bit data transfer by the main CPU, DMA and bus master devices.

·                     An efficient synchronous data transfer mechanism, permitting single transfers as well as high-speed burst transfers.

·                     Allows 32-bit memory addressing for the main CPU, Direct Memory Access (DMA) devices and bus master cards.

·                     Shareable and/or ISA-compatible handling of interrupt requests.

·                     Automatic steering of data during bus cycles between EISA and ISA masters and slaves.

·                     33MB/second data transfer rate for bus masters and DMA devices.

·                     Automatic configuration of the system board and EISA expansion cards.

 

 

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